A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
Metrics
Affected Vendors & Products
References
History
Wed, 12 Nov 2025 21:15:00 +0000
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| Weaknesses | CWE-266 | |
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cvssV3_1
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Wed, 12 Nov 2025 13:00:00 +0000
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| First Time appeared |
Chipsalliance
Chipsalliance rocket-chip |
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| Vendors & Products |
Chipsalliance
Chipsalliance rocket-chip |
Mon, 10 Nov 2025 20:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Description | A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability. | |
| References |
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Status: PUBLISHED
Assigner: mitre
Published: 2025-11-10T00:00:00.000Z
Updated: 2025-11-12T20:39:11.448Z
Reserved: 2025-10-27T00:00:00.000Z
Link: CVE-2025-63384
Updated: 2025-11-12T20:38:58.424Z
Status : Awaiting Analysis
Published: 2025-11-10T20:15:49.013
Modified: 2025-11-12T21:15:52.220
Link: CVE-2025-63384
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